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naja-scope
Lets AI agents explore elaborated SystemVerilog/Verilog designs (RTL or gate-level netlists) without pasting RTL into context: trace signal fan-in/fan-out, walk module hierarchy, and jump to exact `file:line` source, backed by the najaeda netlist engine.
Topics: Developer Tools
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See the repository for installation instructions: https://github.com/najaeda/naja-scope
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